Patent Literature 1 listed below describes a background technique in the technical field. The document describes as a technical problem that a bus arbitration device is obtained which can perform real-time processes within a predetermined duration, as well as which can secure data communication performance without unnecessarily increasing data access amounts with respect to shared memories when real-time processes are performed. The document further describes as a solution to the problem that, when real-time processes are performed, a priority for accessing a shared memory 15 of a CPU 11 is configured to be higher than that when non-real-time processes are performed, and that if the priority of the CPU 11 is high, a bus arbitration is performed so that the maximum burst length for accessing the shared memory 15 is configured to be shorter than that in normal cases (refer to the abstract).